The TAU series of workshops provide
an informal forum for practitioners and researchers working on temporal
aspects of digital systems to disseminate early work and
engage in a free discussion of ideas. The sixteenth in the TAU
series, the TAU 2009 workshop
invites submissions from all areas related to the timing properties of
digital electronic systems,
including but not limited to:
Formal
theories and methods
System-level timing
Transistor-level
timing
Circuit-level timing
Sensitivity analysis
Full custom design
analysis
Integrated functional-temporal analysis
Incremental analysis
Timing issues in low power design
Power-delay trade-offs
Adjacent line switching and
coupling
Delay models and
metrics
Layout impact on timing
Timing-driven layout optimization |
Timing-driven synthesis and re-synthesis
Circuit optimization
Uncertainty-based
analysis
Incorporation of RETs in
timing
Reliability impact on
performance
Process &
environmental variation models
Statistical analysis
technique
Clocking,
synchronization, and
skew
Clock domains,
static/dynamic logic
Novel clocking
schemes
Special circuit
families
Asynchronous systems
Timing implications of emerging technologies
|
All papers must be submitted
electronically. Submissions are limited to 6 pages in the double column
proceedings format. TAU is a workshop aimed at fostering a high level
of professional interaction, not a conference. Copies of papers
will be provided to the attendees, but the proceedings will not be
published by the ACM or the IEEE. Therefore, accepted papers can
still be submitted to other conferences and journals. The
intent of the workshop is to encourage the vigorous and unfettered
discussion of the latest ideas in the field. |
